In the design of integrated circuits, memory devices in a customer design are mapped to memory resources on an integrated circuit layout pattern. Depending on the technology, there may be a large number of different ways in which the memory can be mapped or “tiled” to the memory resources.
It is customary for the integrated circuit manufacturer to provide the customer with various tools and models for assisting the customer in designing or customizing an integrated circuit for a particular application. Some integrated circuits have several different types of memory resources and can include large arrays of memory elements. Since the customer memory often can be mapped to the memory resources in a variety of different ways, the process of generating a timing model of the customer memory for a particular mapping can be come very difficult and may require design tools that process large amounts of data and have long processing times.
Processes and apparatus are therefore desired for generating memory timing models in an efficient manner.